Memory subsystems can be a significant performance bottleneck to achieving the performance potential of a computing system. While one solution to this bottleneck would be to use primarily only very fast memory in a computer system, such as static random-access memory, the cost of such memory renders this potential solution prohibitive. In order to balance cost with system performance, memory subsystem architecture is typically organized in a hierarchical structure, with faster expensive memory operating near the processor at the top, slower less expensive memory operating as storage memory at the bottom, and memory having an intermediate speed and cost, operating in the middle as system memory.
Recent developments in persistent memory technology have begun to erode the performance distinction between the intermediate system memory tier and the bottom storage memory tier. The hierarchical distinction between system memory and storage memory remains, however, due to traditional memory subsystem architecture.